Floating point processors enhance the performance of arithmetic computations within a computer by serving a dedicated purpose directed to performing mathematical operations on numbers with large mathematical ranges. Numbers are expressed and stored in a storage format 5, shown in FIG. 1, having a sign field 5a, an exponent field 5b, and a fraction field 5c (also known as, mantissa field). Generally, as shown in both the exponent and fraction fields 5b, 5c, the binary bits run left to right from the most significant bit (msb) to the least significant bit (lsb). In the early days of floating point processor development, floating point processors were implemented with numerous discrete electronic logic elements on separate cumbersome circuit boards within a computer. In the mid 1980's as development progressed and became more sophisticated, floating point processors were placed on separate microchips, or co-processors, configured to be interfaced to and generally adjacent a microprocessor of the computer. Finally, at present, floating point processors are being implemented within microprocessors themselves, resulting in a need to further substantially enhance the performance and latency requirements of circuits which provide floating point functionality.
Rounding in a floating point processor is considered a complex logic problem. It involves eliminating data bits of lost precision. Data bits of lost precision are those additional bits which are generated during floating point operations and which must be eliminated so that the floating point processor can output a result in the proper storage format. Moreover, rounding may be performed using a wide variety of methodologies. In this regard, see "IEEE Standard for Binary Floating Point Arithmetic," Aug. 12, 1985, which sets forth the American National Standard (ANSI/IEEE Std. 754-1985) for binary floating point arithmetic. See also J. T. Coonen, "An Implementation Guide to a Proposed Standard for Floating Point Arithmetic," IEEE Computer, pp. 68-78, January 1980. The American National Standard requires at least the following rounding schemes within a floating point processor: (1) round-to-nearest, (2) round-toward-positive-infinity (+.infin.), (3) round-toward-negative-infinity (-.infin.), and (4) round-toward-zero. Briefly described, in scheme 1, any number having a lost precision which is greater than 1/2 of a least significant bit, or "1/2 lsb," is rounded up; any number having a lost precision which is less than 1/2 lsb is rounded down; and any number having a lost precision which is exactly equal to 1/2 lsb is rounded either up or down in order to ultimately achieve an even number (i.e., ending in zero). In scheme 2, a number is always rounded toward positive infinity, i.e., up if a positive number and down if a negative number. In scheme 3, a number is always rounded toward negative infinity, i.e., up if a negative number and down if a positive number. Finally, in scheme 4, a number is truncated.
The American National Standard further defines four particular floating point formats. A single format comprises one sign bit, eight exponent bits, and twenty-three fraction bits. A double format comprises one sign bit, eleven exponent bits, and fifty-two fraction bits. Further, both the single and double formats can be extended. In the single extended format, there is one sign bit, at least eleven exponent bits, and at least forty-three fraction bits. Finally, in the double extended format, there are one sign bit, at least fifteen exponent bits, and at least seventy-nine fraction bits.
The basic architecture for a floating point processor 11 is illustrated in FIG. 2. Binary floating point inputs A, B, denoted by reference numerals 12, 14, respectively, are mathematically combined by the floating point processor 11 in order to provide a resultant binary floating point output R, denoted by reference numeral 16. Floating point operations can be in the form of unary operations where only one binary number is operated upon or in the form of binary operations where two binary numbers are mathematically combined. For instance, a unary operation would be a square root operation, a cosine operation, or a conversion from one floating point format to another. Examples of binary operations include addition, subtraction, multiplication, and division. When the floating point processor 11 performs a unary operation on a single floating point number, the floating point number is input as one of the floating point inputs A, B while the other floating point input B, A is set to a constant, such as zero.
The floating point processor 11 comprises sign logic 18, exponent logic 22, and significand logic 24. The significand logic 24 takes the fractions FA, FB and converts them to respective significand formats, which are operated upon by the processor 11. A significand format 6 is illustrated in FIG. 1. As shown, the significand format includes not only the fraction field, but also hidden bits (bits V, N) to the left of the binary point and several lost precision bits (bits G, R, S) to the right of the fraction's lsb (bit L). As shown in FIG. 1, the V, N, Q, L, G, R, S bits are denoted by respective reference numerals 6a-6g. The Q, L bits 6c, 6d are successive lsb's of the fraction 5c. The N bit 6b is an additional msb of the fraction 5c. The V bit 6a is a carry out from the N bit 6b. The G bit 6e is known as a guard bit. The R bit 6f is known as a round bit. Finally, the S bit 6g is known as a sticky bit.
Significant to the discussion in this document, the significand logic 24 comprises a carry propagate adder 26 followed by a post normalizer 27 which includes an incrementer 28 for operating on the fractions FA 12' and FB 14' to derive a resultant fraction FR 16'. In general, the normalizer 27 is disposed for shifting and rounding digits in the result which is output by the adder 26. Shifting digits is necessary to preserve a proper fractional part. Moreover, the incrementer 28 is disposed for incrementing, or adding a logic high ("1" in Boolean logic), if necessary during the rounding process.
A specific example of a floating point processor utilizing an incrementer is described in S. Waser and M. J. Flynn, Introduction to Arithmetic for Digital Systems Designers, pp. 106-107, 123-124, 206-208, 1st Edition, 1982, which description is incorporated herein by reference as if set forth in full hereinbelow. In the floating point processor disclosed in the foregoing textbook, a dedicated circuit and algorithm is used for performing both addition and subtraction, while another dedicated circuit and algorithm is used for performing both multiplication and division.
As mentioned, the incrementer 28 increments the significand if necessary during the rounding process. In order to increment a binary number, a carry propagation must occur across the entire width of the corresponding significand. Such an operation undesirably adds significant delay to the overall operation of the floating point processor. Thus, the use of an incrementer in a floating point processor solves the complex logic problem of rounding at the expense of performance and latency.